Laterally diffused metal oxide semiconductor (LDMOS) devices are used in many different types of applications including cellular telephones as RF power amplifiers. In cellular applications, though, LDMOS devices are known to deplete battery life quickly due to its need for high voltage and high frequency.
In LDMOS devices, an N-well is fabricated in a substrate using a mask and implantation processes. A tapered gate structure is formed over the N-well, with the tapered portion of the gate structure aligning with an edge of the drift region and the N-well, itself, e.g., also referred to as drain well to step-oxide spacing (D). As one of skill in the art would understand, the thicker portion of the underlying dielectric material of the gate structure is a drain region and the thinner portion of the underlying dielectric material of the gate structure is a source region. A P-well is formed in the substrate, adjacent to the source region. The distance between the P-well and the N-well is a drain well spacing (E).
The structures of the conventional LDMOS device are not self-aligned and hence do not scale very well. That is, for example, the P-well and the N-well and hence the critical dimensions “D” and “E” are non-self-aligned, resulting in difficulties with scaling of such features. For example, device pitch (hence specific on-resistance (Ron, SP)) and breakdown voltage are limited by photolithography process, such as the body to drain well spacing (E) and the drain well to step-oxide spacing (D). In more specific examples, as the devices are scaled down, misaligned occurs with the critical dimensions “E” and “D”, hence affecting device performance including breakdown voltage, tunneling effects, etc.